Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems. Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data must be periodically refreshed in order to be retained.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits.
An example of a conventional SRAM cell is shown in FIG. 1. In this example, SRAM cell 2 is a conventional six-transistor (6-T) static memory cell 2, which in this case is in the jth row and kth column of a memory array. SRAM memory cell 2 is biased between the voltage on power supply line Vdda and a ground reference voltage Vssa. SRAM memory cell 2 is constructed in the conventional manner as a pair of cross-coupled complementary MOS (CMOS) inverters, one inverter of series-connected p-channel load transistor 3a and n-channel driver transistor 4a, and the other inverter of series-connected p-channel load transistor 3b and n-channel transistor 4b; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. The common drain node of transistors 3a, 4a constitutes storage node SNT, and the common drain node of transistors 3b, 4b constitutes storage node SNB, in this example. N-channel pass-gate transistor 5a has its source/drain path connected between storage node SNT and bit line BLTk for the kth column, and n-channel pass-gate transistor 5b has its source/drain path connected between storage node SNB and bit line BLBk. The gates of pass-gate transistors 5a, 5b are driven by word line WLj for this jth row in which cell 2 resides.
In operation, bit lines BLTk, BLBk are typically precharged by precharge circuitry 7 to a high voltage Vddp (which is at or near power supply voltage Vdda) and are equalized to that voltage; precharge circuitry 7 then releases bit lines BLTk, BLBk to then float during the remainder of the access cycle. To access cell 2 for a read operation, word line WLj is then energized, turning on pass-gate transistors 5a, 5b, and connecting storage nodes SNT, SNB to bit lines BLTk, BLBk. The differential voltage developed on bit lines BLTk, BLBk is then sensed and amplified by a sense amplifier. In a write operation, typical modern SRAM memories include write circuitry that pulls one of bit lines BLTk, BLBk low (i.e., to a voltage at or near ground voltage Vssa), depending on the data state to be written. Upon word line WLj then being energized, the low level bit line BLTk or BLBk will pull down its associated storage node SNT, SNB, causing the cross-coupled inverters of addressed cell 2 to latch in the desired state.
As known for years in the art, CMOS structures such as memory arrays including CMOS SRAM cell 2 and the like are inherently vulnerable to a condition known as “latchup”. Integrated circuits that incorporate p-channel and n-channel MOS field-effect transistors (MOSFETs) near one another necessarily include adjacent regions of n-type and p-type doped silicon that form a p-n-p-n structure. Under certain conditions, those alternating adjacent p-n-p-n regions can operate as a “thyristor”, or silicon-controlled rectifier (“SCR”), circuit in which an n-p-n bipolar transistor is paired with a p-n-p bipolar transistor in a feedback arrangement.
FIG. 2a is an electrical schematic of a well-known SCR circuit, based on p-n-p bipolar transistor 10 and n-p-n bipolar transistor 12. In this case, the emitter of transistor 10 is connected to the anode of the SCR, its base is connected to the collector of transistor 12 and, via resistor 13, to power supply voltage Vdd. The base of transistor 12 is connected to the collector of transistor 10 and, via resistor 11, to ground Vss. The emitter of transistor 12 is connected to the cathode of the SCR. In operation, power supply voltage Vdd is biased positive relative to ground Vss. If the base-emitter junction of transistor 10 becomes forward-biased, due to a sufficiently high voltage at anode A, transistor 10 conducts current into the base of transistor 12, forward-biasing its base-emitter junction and causing conduction that flows into the base of transistor 10. Either of transistors 10, 12 can initiate this conduction. This positive feedback results in a relatively large current conducted between anode A and cathode C. As known in the art, the positive feedback effect is so rapid that a “snapback” in the current-voltage characteristic at the anode, appearing as “negative resistance” as the anode current continues to increase as the anode voltage decreases. So long as the anode voltage remains above a certain voltage (i.e., the “hold” voltage), the SCR will conduct a relatively large current.
These p-n-p-n structures inherent in conventional CMOS integrated circuits form a parasitic SCR that can be triggered into a latchup condition by the coupling of noise to certain nodes during the operation of the integrated circuit. The massive current conducted in such a latchup condition can cause operating failure of the integrated circuit or, in the worst case, an overcurrent condition that physically destroys the integrated circuit.
By way of further background, Boselli et al., “Latch-up in 65 nm CMOS Technology: A Scaling Perspective”, 43rd Annual International Reliability Physics Symposium (IEEE, 2005), pp. 137-44, incorporated herein by reference, describes the behavior of latchup tendencies over the 180 nm, 130 nm, 90 nm, and 65 nm “technology nodes” (i.e., the typical distance between identical features in adjacent memory cells in an array for a given manufacturing technology). As described in that paper, latchup susceptibility appears to decrease as feature sizes shrink. In particular, as the technology scales to smaller features, the latchup feedback loop appears to weaken, the voltage differential between the SCR “hold” voltage and the power supply voltage (e.g., Vdd) appears to increase, and the temperature dependence of the onset of latchup appears to decrease. All of these observed tendencies indicate that the latchup condition is becoming more difficult to trigger and sustain as CMOS technology scales over time.
It has also been observed that these p-n-p-n structures, when present in CMOS memories such as SRAMs, are vulnerable to single-event-upset (SEU) events. As known in the art, SEU events are typically caused by particles impacting the integrated circuit and causing ionization that results in free charge near a logic node or memory cell. This free charge can forward bias the base-emitter junction of one of the parasitic bipolar transistors, triggering thyristor action and, in the case of an SRAM cell, potentially changing its stored data state. The bit error rate due to SEUs can become sufficiently high that conventional error-correction techniques cannot correct for all errors, particularly if the SEUs cause multiple cell upsets (MCUs) in the same stored data word. The probability of MCUs tends to increase as minimum device feature sizes scale smaller, especially for feature sizes in the deep-sub-micron domain (e.g., 65 nm).
FIG. 2b illustrates a cross-section of a typical conventional CMOS structure, such as may be encountered in an array of SRAM cells 2, and in which a parasitic SCR resides. The structure of FIG. 2b is constructed according to a twin-well technology, with n-type well 16 and p-type well 18 disposed at the surface of p-type substrate 14. N-type well 16 is a relatively lightly-doped region into which p-channel MOS transistors are formed; conversely, p-type well 18 is a relatively lightly-doped region into which n-channel MOS transistors are formed. The structure of FIG. 2b may alternatively correspond to a single n-well technology, if p-well 18 is not separately implanted but is instead merely a surface portion of p-type substrate 14. Shallow trench isolation dielectric structures 15 define several active regions of the surface of wells 16, 18, each of which includes a relatively heavily-doped region at the surface. In this example, n-well 16 includes heavily-doped n+ region 17n and heavily-doped p+ region 17p, and p-well 18 includes heavily-doped n+ region 19n and heavily-doped p+ region 19p. As known in the art, heavily-doped regions 17n, 19p are within wells 16, 18, respectively, of the same conductivity type and thus serve as well contacts (n+ region 17n at power supply voltage Vdd and p+ region 19p at ground Vss). In this construction, p+ region 17p corresponds to the emitter of p-n-p transistor 10 in the parasitic SCR, n+ region 19n corresponds to the emitter of lateral n-p-n transistor 12, n+ region 17n is the base contact of transistor 10 and the collector contact of transistor 12, and p+ region 19p is the base contact of transistor 12 and the collector contact of transistor 10. Resistor 11 of the parasitic SCR is constituted by the lateral resistance of well 18 and substrate 14, and resistor 13 is the lateral resistance of well 16.
Considering this construction, thyristor behavior in the CMOS structure of FIG. 2b can be triggered by noise coupling, or by free charge due to an SEU, of sufficient magnitude to forward bias the junctions at either (or both) of the emitter nodes at p+ region 17p and n+ region 19n. Because of the junction capacitance of regions 17p, 19n, dV/dt induced current can be injected into the base of one of transistors 10, 12, respectively. If the lateral resistance of the corresponding resistor 11, 13 is too high, the base-emitter junction of the transistor 10, 12 receiving the injection current can forward bias, initiating base current in the opposite parasitic device that, through the positive feedback mechanism described above, results in a latchup state with large current conducted from anode A (p+ region 17p) to cathode C (n+ region 19n).
The risk of latchup and SEUs in conventional CMOS integrated circuits is minimized by ensuring that well contacts are present at a sufficient spatial frequency. These well contacts ensure that the base-emitter junctions of the parasitic bipolar transistors in the structure are not significantly forward-biased. It has been observed that the latchup and SEU threshold of the structure of FIG. 2b is largely determined by the resistance of parasitic resistor 13 in n-well 16, which depends on the spacing of well-tie n+ regions 17n (which receive power supply voltage Vdd) within n-wells 16. Close spacing of well-tie n+ regions 17n will keep that well resistance low, to limit the voltage drop caused by SEU or noise current to a level that maintains the base-emitter voltage of parasitic p-n-p transistor 10 below its forward bias threshold.
FIG. 2c illustrates, in cross-section, a conventional CMOS structure with improved latchup and SEU tolerance relative to that of FIG. 2b. The structure of FIG. 2c is similar to that of FIG. 2b, including both n-well 16 and p-well 18. However, the structure of FIG. 2b also includes deep n-well region 16D, which is an n-type doped region of the structure that is formed, by ion implantation, at a depth below that of n-well 16 and p-well 18. In conventional SRAMs and other integrated circuits similarly constructed, deep n-well region 16D underlies the entirety of the CMOS memory array or other operative region, and functions to connect each of n-wells 16 to one another in that region. For purposes of SEU and latchup prevention, deep n-well 16D reduces the resistance of base resistor 13 in parasitic p-n-p transistor 10, by effectively increasing the cross-sectional area of the semiconductor structure defining resistor 13. In addition, the additional junction capacitance at n-well 16 is increased by the provision of deep n-well 16D; as known in the art, increased capacitance at the node receiving the free charge (in an SEU) or noise will reduce the resulting voltage at that node, inhibiting the forward biasing of the parasitic base-emitter junction and thus increasing the amount of charge required to trigger the parasitic thyristor from p-n-p transistor 10.
However, it has been observed, in connection with CMOS structures such as that of FIG. 2c, that the presence of deep n-well 16D tends to increase the resistance of parasitic base resistor 11 and reduce the parasitic capacitance of p-well 18, relative to that of parasitic base resistor 13 and n-well 16. These effects increase the susceptibility of n-p-n transistor 12 to initiate latchup in response to noise or an SEU event. As a result, it is the frequency and spacing of well-tie p+ regions 19p within p-wells 18 that determines the effective well or substrate resistance of parasitic resistor 11, and thus the sensitivity of the structure to latchup and SEU.
FIG. 3 illustrates the layout of memory cell array 20 (or, alternatively, one memory cell array block of a multiple-block memory cell array 20, as the case may be) in a conventional integrated circuit. In this example, memory cell array 20 includes two half-arrays 22, each of which contain a number of SRAM cells 2 arranged in rows and columns. In this conventional example, SRAM cells 2 are realized as CMOS circuits, with structures corresponding to those described above in connection with FIGS. 1, 2b, and 2c (including at least one well region (e.g., n-well 16 containing p-channel transistors 3a, 3b, and perhaps deep n-well 16D). As shown in FIG. 3, dummy cell rows 23 are provided on opposite ends of memory cell array 20. These dummy cell rows 23 are constructed similarly as SRAM cells 2 within half-arrays 22, but are not connected or otherwise operable as memory cells. Dummy cell rows 23 are instead provided to maintain photolithographic regularity for the outermost cells 2 in half-arrays 22, as conventional for integrated circuits realized by sub-micron feature sizes. Typically, well contacts in the form of well-tie regions 17n, 19p are provided within dummy cell rows 23, contacted by overlying metal conductors biased at the appropriate power supply or ground voltage (e.g., voltages Vdd, Vss, etc.) in operation.
The conventional layout of FIG. 3 also includes strap row 24 disposed between half-arrays 22 as shown. Strap row 24 also contains “top-side” well contacts to either or both of n-wells 16 and p-wells 18, to which overlying metal conductors route the appropriate power supply or ground voltage (e.g., voltages Vdd, Vss, etc.). In this arrangement, in which strap row 24 runs vertically (in the view of FIG. 3), wells 16, 18 would run horizontally (in the view of FIG. 3), to minimize the spacing of well-tie regions 17n, 19p. It is contemplated that, of course, additional strap rows 24 may be necessary within memory cell array 20, depending on the particular layout and manufacturing parameters, on the size of memory cell array 20.
Of course, additional chip area is required for the realization of each strap row 24 and each dummy cell row 23 to be of sufficient size to accommodate well region contacts. Particularly in those integrated circuits with substantial chip area already consumed by multiple instances of memory cell array 20, the provision of one or more strap rows 24 within each memory cell array 20 to avoid latchup can amount to a significant cost. It has also been observed that conventional well contacts, and thus conventional strap rows 24 and dummy cell rows 23, do not scale with reductions in gate level feature sizes (i.e., transistor gate lengths), considering that these well contacts tend to be defined by metal conductor pitch, rather than by gate level features. Therefore, as minimum feature sizes continue to be reduced by advances in photolithography and other processing technologies, the fraction of the overall chip area consumed in order to make well region contacts for the array grows. In some modern integrated circuits including memory cell arrays 20, a chip area penalty for array well region contacts of as high as 3% has been observed at the current state-of-the-art technology node.
By way of further background, copending and commonly assigned application Ser. No. 13/558,003, filed Jul. 25, 2012, entitled “Efficient Static-Random Access Memory Layout”, incorporated herein by this reference, describes a complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with no well contacts within the memory array, and in which wells of either or both conductivity types may electrically float during operation of the memory. An example of such a memory constructed with a deep n-well underlying the memory array is disclosed.